1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a new and improved manufacture process by first selecting a known good substrate (KGS) by first testing a substrate mounted with a most performance-demanding chip before testing and mounting additional multiple chips onto the substrate.
2. Description of the Prior Art
There is a challenge faced by those applying the multiple-chip module (MCM) technology to package multiple electronic chips into a single module employing a substrate formed with interconnecting traces with the traces checked only with visual inspections or a simplified open-short test. This challenge arises from the fact that the substrate now formed with interconnected traces when mounted on with multiple chips may not function appropriately to satisfy the requirements of high frequency high speed performance, particularly the substrate is not functionally tested. The issues are not obvious for conventional MCM when the packing density and performance level are not as stringent as newer MCM designs where low K dielectric coefficients are required with copper metallization for packaging integrated circuit (IC) chips with feature sizes of 0.1 micron or smaller. The total system performance with higher packing density to achieve higher operational speed will eventually limited by signal integrity transmitted over the interconnecting traces rather than the integrated circuit (IC) chips.
Conventional method of manufacturing a MCM assembly without first electrically testing the substrate together with at least one IC chip, often causes significant reduction in production yield due to the performance mismatches between the substrate and the chips mounted onto the substrate. Failures of the substrate or any one of the multiple chips can also affect production yield. Referring to FIGS. 1A to 1D for a top view of a substrate and a top view, side cross sectional view and bottom view respectively of a conventional MCM assembly that includes three IC chips. FIG. 1E is a flow chart for illustrating the process flow for manufacturing the MCM assembly shown in FIGS. 1A to 1C. The MCM substrate supports the interconnecting traces and the ball grid array as that shown in FIG. 1C is manufactured. The first, second, and third IC chips are mounted onto the substrate, with a top view shown in FIG. 1B, using a chip on board (COB) process. As that shown in FIGS. 1B and 1C, standard wire bonding processes are carried out for packaging direct-attached multiple chips and the substrate. As shown in FIG. 1B, an encapsulation is applied to cover multiple chips and to protect the bonding wires under the encapsulation. Then a burn-in and functional tests are performed to determine whether the MCM assembly would pass or fail the tests. At this point, failure of the substrate or anyone of the multiple chips can lead to the failure of the MCM assembly. Employment of a substrate without actual functional test as now commonly implemented in the manufacturing process of the MCM assemblies can therefore cause significant reduction of production yield, particularly when there are more stringent requirements now imposed on the performance of the substrate as well as on the chips.
For the purpose of increasing the production yield, FIG. 1F is a flow chart of showing another process flow by first assembling, burning testing each of the multiple chips as chip size package (CSP). These tested and known-good CSP chips are then mounted on a substrate provided with BGA or a land-grid array. This process is most costly and production can be improved by assuring only known good dies are employed. This method however can still be impacted by using a substrate due to the fact that the substrate is untested and probably cannot achieve the performance requirements with higher speed and packaging density are now required for the MCM assembly.
Therefore, a need still exits in the art to provide an improved configuration and procedure for testing and packaging the multiple chip modules to minimize the adverse impact on production yield due to inadequate performance of the substrate after multiple chips mounted are mounted. More specifically, an improved process and configuration to assure a substrate can properly function with a most performance demanding chip must be first tested to resolve the difficulties of low production yield as now encountered by the conventional methods of MCM manufacture.
It is therefore an object of the present invention to provide an improved configuration and procedure for testing and packaging the multiple chip modules (MCMs). The improved MCM package configuration provide a process flow to fully test the substrate with the most performance-demanding chip mounted and known good tested packages to assure the substrate can function properly. The process flow and configuration ensure production yield is improved without unduly increasing the production costs. The difficulties and limitations as that encountered in the prior art are resolved.
Specifically, it is an object of the present invention to provide an improved MCM configuration and procedure for testing and packaging multiple chips as MCM assemblies by employing a specially configured substrate. The substrate is provided for first mounting a most performance-demanding chip and then using a set of footprints formed on the substrate for clamping remainder of multiple chips for carrying out a functional MCM test to assure the substrate is working properly. The functionality and performance of the substrate can be more realistic tested before the final MCM assembly is manufactured and tested. The problems encountered by the prior art in using an untested substrate are therefore resolved.
Briefly, in a preferred embodiment, the present invention comprises a substrate having a top surface for mounting multiple integrated circuit (IC) chips. The substrate includes a first footprint comprising a plurality of electrical contacts disposed on the top surface for mounting a most performance-demanding IC chip thereon. The substrate further includes a set of substrate testing footprints comprising a plurality of package mounting and testing electrical contacts for temporarily mounting a plurality of testing packages to conduct a functional MCM test for the substrate mounted with the most performance-demanding IC chip and the testing packages. In a preferred embodiment, the substrate further includes a plurality of solder balls disposed on a bottom surface of the substrate opposite the top surface. In a preferred embodiment, the substrate further includes a plurality interconnecting traces interconnected between the electrical contacts of the first footprint and the set of substrate testing footprints. In a preferred embodiment, the first footprint for mounting the most performance-demanding IC chip includes a plurality of electrical contacts arranged for wire-bonding the most performance-demanding IC chip onto the substrate. In a preferred embodiment, the first footprint for mounting the most performance-demanding IC chip includes a plurality of electrical contacts arranged for disposing a packaged IC chip as the most performance-demanding IC chip onto the substrate. In a preferred embodiment, the set of substrate testing footprints comprising at least a set of chip-size package (CSP) electrical contacts for temporarily mounting at least a CSP testing package to conduct a functional MCM test for the substrate mounted with the most performance-demanding IC chip and the testing packages. In a preferred embodiment, the set of substrate testing footprints comprising at least a set of flip chip package (FCP) electrical contacts for temporarily mounting at least a flip-chip testing package to conduct a functional MCM test for the substrate mounted with the most performance-demanding IC chip and the testing packages. In a preferred embodiment, the set of substrate testing footprints comprising at least a set of signal generator electrical contacts for temporarily mounting at least a signal generator to conduct a functional MCM test for the substrate mounted with the most performance-demanding IC chip and the testing packages. In a preferred embodiment, the first footprint for mounting the most performance-demanding IC chip includes a plurality of electrical contacts arranged for mounting the most performance-demanding IC chip as a chip-size package onto the substrate. In a preferred embodiment, the first footprint for mounting the most performance-demanding IC chip includes a plurality of electrical contacts arranged for mounting the most performance-demanding IC chip as a flip-chip package onto the substrate.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various drawing figures.